Munich, Germany – June 2 nd, 2020 – Codasip GmbH, the leading supplier of configurable RISC-V ® embedded processor IP, announced today that the Codasip SweRV Support Package has been extended to ...
Western Digital has announced that it's completed work on its Swerv RISC-V CPU core and has published the register-transfer level (RTL) abstraction of the design. Publishing the RTL code allows other ...
Die Hardwarebeschreibung der SSD-Controller SweRV von Western Digital ist nun als Open Source verfügbar. Die Controller hatte das Unternehmen erstmals Ende vergangenen Jahres vorgestellt. Diese ...
In mid-May, CHIPS Alliance announced the open sourcing of the SweRV Core EH2 and SweRV Core EL2 designed by Western Digital. These cores, as well as the earlier EH1, are now supported by Codasip’s ...
Munich, Germany – April 23 rd, 2020 – Codasip GmbH, the leading supplier of configurable RISC-V ® embedded processor IP, announced today the official release of its new product, the Codasip SweRV Core ...
Western Digital announced at the RISC-V Summit three new open-source innovations designed to support Western Digital's internal RISC-V development efforts and those of the growing RISC-V ecosystem. In ...
Mit SweRV stellt Western Digital einen neuen CPU-Kern vor, welcher speziell auf die Bedürfnisse von SSD-Controller zugeschnitten ist und auf der offenen RISC-V-Architektur basiert. Im Vergleich zu den ...
Western Digital hat einen auf der offenen RISC-V-Architektur basierenden CPU-Kern entwickelt, den SweRV (öffnet im neuen Fenster). Wofür das steht, wissen wir zwar nicht – laut Hersteller soll das ...
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