IEEE

Multi-standard low-power DDR I/O circuit design in 7nm CMOS process

Abstract: This paper presents novel circuit techniques to implement DDR I/O circuit design that can support multiple low-power standards in a state-of-art 7nm CMOS finfet process. Hybrid pull-up ...
IEEE

System-level clock jitter modeling for DDR systems

Abstract: As DDR speed continues to increase, uncorrelated timing jitter becomes a significant portion of channel timing budget. The dominant component of uncorrelated timing jitter comes from power ...